Send your resume to email@example.com if you are interested in following Engineering Manager opening. While sending the resume, kindly do mention the "Job Id" (given below) and the following information:
- Current CTC
- Expected CTC
- Time to join (if offered)
- Willingness to relocate to Bangalore
- Preferred Job Locations (In India)
IMP NOTE: Candidate should have good experience (min 7 years) in VLSI/Semiconductor industry.
Job Id - EM_CDS
Job Location - Bangalore, India
Experience - Min 7 years of experience in VLSI / Semiconductor Industry
Qualification Required - Masters Degree in Electronics Engg - from a reputed Institute
- A technical leadership position - to orchestrate and put together a solid back-end chip-finish flow - with Cadence DFM tools.
- Interact with R&D - for DFM products - and build a seamless chip-finish flows - from P&R to Chip Verification and Chip Optimization, leading to finished chip tape-out
Skills & Experience
- Hands on design experience of 5 years in building SoC chips
- Experience in the post layout physical verification and chip finish flow
- Hands-on on physical verification methodology –DRC/ERC/LVS
- Good understanding on the complete chip finish flow in both custom as well as cell based flow
- P&R to Chip verification and Chip optimization and tape out.
- Layout to verification and parasitic extraction and tape out.
- Good knowledge on the SVRF rule deck
- Working knowledge on Virtuoso and Cadence DFM tools will be an added advantage
Email resume to firstname.lastname@example.org
For any further details call me at +91-9216157361 (Gaurav)